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Verification Methodology Manual for SystemVerilog (Hardback)
  • Verification Methodology Manual for SystemVerilog (Hardback)
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Verification Methodology Manual for SystemVerilog (Hardback)

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£159.99
Hardback 503 Pages / Published: 28/09/2005
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Offers users the first resource guide that combines both the methodology and basics of SystemVerilog

Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly.

Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.

Publisher: Springer-Verlag New York Inc.
ISBN: 9780387255385
Number of pages: 503
Weight: 2000 g
Dimensions: 235 x 155 x 28 mm
Edition: 2006 ed.

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