This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
Publisher: Springer-Verlag New York Inc.
Number of pages: 216
Weight: 1120 g
Dimensions: 235 x 155 x 14 mm
Edition: 2003 ed.
From the reviews:
"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. ... The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)
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