Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
Publisher: Springer-Verlag New York Inc.
Number of pages: 564
Weight: 1126 g
Dimensions: 254 x 178 x 31 mm
Edition: Softcover reprint of the original 1st ed. 199
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