Logic Synthesis and Verification Algorithms (Paperback)
  • Logic Synthesis and Verification Algorithms (Paperback)
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Logic Synthesis and Verification Algorithms (Paperback)

(author), (author)
£64.99
Paperback 564 Pages / Published: 10/02/2006
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This book blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.

Publisher: Springer-Verlag New York Inc.
ISBN: 9780387310046
Number of pages: 564
Weight: 1830 g
Dimensions: 235 x 155 x 30 mm
Edition: 1996 ed.

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