Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to create this authoritative first book on the essentials of programming for this new architecture and these new products. This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture.
Publisher: Elsevier Science & Technology
Number of pages: 432
Weight: 730 g
Dimensions: 235 x 191 x 25 mm
"Reinders and Jeffers have written an outstanding book about much more than the Intel (R) Xeon Phi (TM). This is a comprehensive overview of the challenges in realizing the performance potential of advanced architectures, including modern multi-core processors and many-core coprocessors. The authors provide a cogent explanation of the reasons why applications often fall short of theoretical performance, and include steps that application developers can take to bridge the gap. This will be recommended reading for all of my staff." -James A. Ang, Ph.D. Senior Manager, Extreme-scale Computing, Sandia National Laboratories "The authors' consummate knowledge of the architecture shines through in this excellent introduction to the fundamentals of programming for the Intel (R) Xeon Phi (TM) coprocessor." I highly recommend this engaging treatise to programmers interested in effectively utilizing the Intel (R) Xeon Phi (TM) coprocessor." -R. Glenn Brook, Ph.D., Chief Technology Officer, Joint Institute for Computational Sciences, Director, Application Acceleration Center of Excellence, University of Tennessee / Oak Ridge National Laboratory "The authors have provided a very readable, big-picture introduction to programming the Intel Xeon Phi Coprocessor. By chronicling step-by-step optimizations of several computational kernels, software interfaces are illustrated for getting the most out of key architectural features of the Intel Xeon Phi Coprocessor." -James L. Schwarzmeier, Cray Inc, January 2013." "This book belongs on the bookshelf of every HPC professional. Not only does it successfully and accessibly teach us how to use and obtain high performance on the Intel MIC architecture, it is about much more than that. It takes us back to the universal fundamentals of high-performance computing including how to think and reason about the performance of algorithms mapped to modern architectures, and it puts into your hands powerful tools that will be useful for years to come." -Robert J. Harrison, Institute for Advanced Computational Science, Stony Brook University, from the Foreword
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