Formal Semantics and Proof Techniques for Optimizing VHDL Models (Paperback)
  • Formal Semantics and Proof Techniques for Optimizing VHDL Models (Paperback)
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Formal Semantics and Proof Techniques for Optimizing VHDL Models (Paperback)

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£89.99
Paperback 158 Pages / Published: 26/10/2012
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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Publisher: Springer-Verlag New York Inc.
ISBN: 9781461373315
Number of pages: 158
Weight: 290 g
Dimensions: 235 x 155 x 9 mm
Edition: Softcover reprint of the original 1st ed. 199

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