This book walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process. It covers all CAD/CAE aspects of a SOC design flow and addresses a new topic (DFM/DFY) critical at 90 nm and beyond. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.
Number of pages: 255
Weight: 444 g
Dimensions: 235 x 155 x 15 mm
Edition: Softcover reprint of hardcover 1st ed. 2007
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