Publisher: Springer-Verlag New York Inc.
Number of pages: 414
Weight: 664 g
Dimensions: 235 x 155 x 23 mm
Edition: Softcover reprint of the original 1st ed. 200
From the reviews:
"This book unveils the mystery behind the performance gap between ASIC and Custom design and shows how to close the gap with minimal design effort. A must read for every ASIC or ASSP designer."
(William J. Dally, Professor, Stanford University)
"Most IP core providers must provide high-performance designs within the constraints of an ASIC methodology. I'm optimistic that careful application of the techniques in this book will enable me to design embedded processors that do indeed close `the Gap Between ASIC and Custom'."
(Kees Vissers, Director of Architecture, Trimedia Technologies Inc.)
"This book provides a comprehensive explanation of why ASICs fall so far behind custom ICs in performance, and then shows how better tools, libraries and methodologies can narrow the gap. It's a must read for ASIC designers who want to boost performance - or custom designers who want to speed time to market with ASIC-like design methodologies."
(Richard Goering, EDA Editorial Director, EE Times)
"I've heard there is a price on the authors' heads. Power Users don't like people who give away their secrets."
(Gary Smith, Chief Analyst, Dataquest)
"This book reflects the best research to date on understanding the tradeoffs between full-custom intellectual property blocks and synthesized intellectual-property blocks - a topic we could only touch on in the Reuse Methodology Manual. It is required reading for anyone engaged in system-on-a-chip design."
(Michael Keating, author of the Reuse Methodology Manual, Vice-President, Synopsys)
"Solves one of life's little mysteries[...] It looks like it should become required reading for the IC innovators of this millennium."
(Neil Weste, author of Principles of CMOS VLSI Design, Cisco Systems, Inc.)
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